Instruction Sets and Pipelining

Instruction Sets and Pipelining

The instruction set architecture (ISA) defines the interface between software and hardware — the set of instructions a processor can execute. Pipelining is a technique to execute multiple instructions simultaneously, dramatically improving throughput.

Instruction Set Architecture

The ISA specifies:

• The instruction set — what operations are available
• Addressing modes — how operands are located
• Registers — how many and what they do
• Data types — what sizes/formats are supported
• Instruction format — how instructions are encoded in binary

Machine Code Instruction Format

A typical instruction contains:

Field	Purpose
Opcode	The operation to perform (e.g., ADD, LOAD, BRANCH)
Operand(s)	The data or address to operate on
Addressing mode	How to interpret the operand

Addressing Modes

Mode	Meaning	Example	Use
Immediate	Operand IS the data	ADD #5 (add 5)	Constants
Direct	Operand is the memory address of the data	LOAD 200 (load from address 200)	Simple variable access
Indirect	Operand is the address of an address	LOAD (200) (200 contains the real address)	Pointers, arrays
Indexed	Address = base address + index register	LOAD 200,X (address = 200 + X)	Array traversal
Register	Operand is a register	ADD R1 (add contents of R1)	Fast, internal

CISC vs RISC

Feature	CISC	RISC
Full name	Complex Instruction Set Computer	Reduced Instruction Set Computer
Instructions	Many, complex, variable length	Few, simple, fixed length
Cycles per instruction	Multiple (varies)	Typically 1
Addressing modes	Many	Few
Hardware	Complex, microcode-based	Simple, hardwired control
Code size	Smaller (each instruction does more)	Larger (more instructions needed)
Pipelining	Harder (variable instruction length)	Easier (fixed format)
Example	x86 (Intel/AMD desktop CPUs)	ARM (phones, tablets, Raspberry Pi)

Modern reality: Most modern x86 processors internally translate CISC instructions into RISC-like micro-operations, blurring the distinction.

The Fetch-Decode-Execute Cycle

Every instruction goes through:

1. Fetch: PC → MAR → Memory → MDR → CIR; PC incremented

2. Decode: Control unit decodes the opcode in CIR; identifies operands and addressing mode

3. Execute: ALU performs the operation; result stored in register or memory

Key registers:

Register	Purpose
PC (Program Counter)	Address of next instruction to fetch
MAR (Memory Address Register)	Address being accessed in memory
MDR (Memory Data Register)	Data read from / written to memory
CIR (Current Instruction Register)	The instruction being decoded/executed
ACC (Accumulator)	Stores ALU results

Pipelining

Pipelining overlaps the stages of multiple instructions, like an assembly line in a factory.

Without pipelining (sequential):

Instruction 1: F D E
Instruction 2:       F D E
Instruction 3:             F D E
Total: 9 clock cycles for 3 instructions

With pipelining:

Instruction 1: F D E
Instruction 2:   F D E
Instruction 3:     F D E
Total: 5 clock cycles for 3 instructions

Throughput: With a k-stage pipeline processing n instructions: total cycles = k + (n − 1), compared to k × n without pipelining.

Speedup approaches k (the number of stages) for large n.

Pipeline Hazards

Pipelining doesn't always work perfectly. Hazards cause stalls ("bubbles"):

1. Data hazard: An instruction needs data that a previous instruction hasn't finished computing.

ADD R1, R2, R3    # R1 = R2 + R3
SUB R4, R1, R5    # needs R1, but ADD hasn't written it yet!

Solutions: Forwarding/bypassing (send result directly), stalling (insert NOPs), compiler reordering.

2. Control hazard (branch hazard): A branch instruction changes the PC, but the next instruction has already been fetched.

BEQ label        # if equal, jump to label
ADD R1, R2, R3   # already fetched — might not need to execute!

Solutions: Branch prediction (guess which way the branch goes), delayed branching, speculative execution.

3. Structural hazard: Two instructions need the same hardware resource at the same time (e.g., both need memory access).

Solutions: Separate instruction and data caches (Harvard architecture), duplicating hardware.

Superscalar and Multi-Core

Superscalar processors have multiple pipelines, executing more than one instruction per clock cycle. They require:

• Multiple ALUs and execution units
• Instruction-level parallelism (ILP) in the program
• Complex scheduling logic

Multi-core processors have multiple independent cores, each with its own pipeline. Parallelism requires software to be written with multiple threads.

Exam Tips

• Know all five addressing modes with a practical example for each
• Be able to trace the fetch-decode-execute cycle naming specific registers at each stage
• Pipelining questions often ask you to draw a timing diagram — use the grid format shown above
• Calculate the speedup from pipelining: cycles_without / cycles_with
• CISC vs RISC is a common comparison question — organise your answer as a table
• For pipeline hazards, name the hazard type, give an example, and state a solution
• Remember: pipelining improves throughput (instructions per second) but not latency (time for one instruction)